First, lets understand what we mean by models. We will restrict this discussion to digital ICs. There are at least three distinct types of models system designers might need.
Signal integrity models are needed to verify that the traces connecting the different parts on the board and across the backplane will carry the signals from chip to chip without introducing so much distortion that the receiver will be unable to correctly interpret its inputs. This type of model is usually supplied in IBIS format but may also be in Hspice or VHDL-AMS. IC companies do a fair job of providing these.
If an IC incorporates JTAG, it should have another type of model that defines the JTAG boundary scan chain. This type of model comes in a language called BSDL and IC companies are quite good at providing them when appropriate.
A third type of model is for functional simulation. A few IC companies do an excellent job providing these, most IC companies are fair to poor at providing them and, some companies do not provide them at all.
Why are simulation models important? What do engineers do with them? How can the IC industry do a better job supplying them?
Simulation models allow design engineers determine if they have connected the chips correctly, are trying to use them correctly, and meet all the timing requirements. They are also used during the development of FPGAs and ASICs for verifying the correctness of the chip’s interfaces. Models may be written in VHDL, Verilog, SystemVerilog, or SystemC. Having these models speeds the design and verification processes, reduces board spins, and helps get the product to market faster.
Many IC companies see functional models as extensions of their datasheets. Many of today’s components are so complex, that it is difficult to be sure all aspects of their operations have been accounted for in the board design. For example, I have seen a board fail to meet customer specifications because the designers overlooked a note on the memory’s datasheet saying the part should not be written to until it had been powered up for 200 microseconds and refreshed 64 times. That contributed to the company losing a very large contract with a major telecom company. The memory vendor did not get any orders from that project.
Most IC companies can do a better job supplying models. Engineers need models that simulate what the chips do at a high level of abstraction. They do not need slow, encrypted RTL models that are left over from product development. RTL models consume too many computer resources during simulation and do not provide warnings about timing violations or protocol errors. Encrypted models are fragile. They must be encrypted differently for each version of each EDA vendor’s simulator. When the design engineer does discover a problem, the opaque encrypted model does little to help him understand what he did wrong. There are also models that require expensive third party licenses. Why would an IC company want such an impediment to engineers trying to design in their products?
My preferred solution is, of course, that all the IC companies contract with FMF for models. Baring that, they are free to borrow our methodology, style, and techniques to provide standards based, open source models that their customers can use without encumbrances. It has all been published and there are a thousand examples available for free download. Just give your customers what they need.
Your work is great, as a test engineer, I have been suffering from the absence of the simulation model for the devices under test. while the simulation model creation may count for 40% of test application develpment time.