Engineers often ask “Do I have to use timing with FMF models?” The answer, as usual, is “It depends”. In most cases, the engineer is working on an ASIC or FPGA which they are simulating at the register transfer level. The FPGA model has no timing, cycle accurate simulation is sufficient so, why should any of the components around it need timing?
If the models being used are only of descrete logic, gates and flip-flops, than backannotation of an SDF file to provide timing values can be skipped. However, if the models are of memories, complex or source synchronous parts, than results may not be cycle accurate without timing.
To turn the question around, why wouldn’t a designer want timing in a simulation? The first answer I hear is that it will slow things down. In my experience, there has been no discernable difference in simulation speed between with and without timing. Next, it is too much trouble. True, it does take a little time to generate the SDF file but, once it is created, it does not have to be changed unless the board-level schematic changes. FMF provides a perl script to read your VHDL netlist and generate an SDF file. It is an automated process.
Finally, timing wrappers can be added to your RTL design. This will not only make your board-level simulations run an order of magnatude faster than using the gate-level representation but, it can also be used to derive the timing constraints needed for the FPGA place and route process. A paper on how to do this was just published on the FMF website at http://www.FreeModelFoundry.com/pdf/Verification_Beyond_Chip.pdf.
As always, your feedback on this or any other topic is welcome.