VHDL vs Verilog Model Footprints

An engineer and user of FMF (www.FreeModelFoundry.com) component models was recently having difficulties simulating a design that included a large amount of memory. His simulations would die during elaboration because his PC did not have enough memory. He was advised by an applications engineer from his simulator vendor that Verilog models would consume less computer… Continue reading VHDL vs Verilog Model Footprints

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