Archive for April, 2007

VHDL vs Verilog Model Footprints

Thursday, April 26th, 2007

An engineer and user of FMF (www.FreeModelFoundry.com) component models was recently having difficulties simulating a design that included a large amount of memory. His simulations would die during elaboration because his PC did not have enough memory. He was advised by an applications engineer from his simulator vendor that Verilog models would consume less computer memory than VHDL models.

This seemed contrary to my personal experience. I wanted to say the applications engineer was wrong but, I hate making a fool of myself in public (again) and did not have the numbers to back me up. I told the engineer I would get the numbers and report back to him.

Which language has the smaller footprint for memory models? I ran some tests to find out. A summary of the results are presented below. A full report is available in a white paper on the FMF website. (more…)