System Verification Blog

This is the sixth and final installment of the FMF/Spansion presentation given at the Flash Memory Summit of August 2008 in Santa Clara California.  If you are just tuning in, the first installment was posted in December 2008.

It has taken a long time but, most IC companies have seen the advantages of providing simulation models of their components.  For engineers who use board-level verification in their design process, vendor provided models facilitate faster, more accurate development and shorter time to market.  Unfortunately, not all vendors are providing models and many of those that do are modeling only a subset of their product lines.

Spansion, on the other hand, is providing models of their entire portfolio of flash memories.  The response from engineers has been enthusiastic.  In 2007, downloads of Spansion flash memory models exceeded 40,000 per month just from the FMF website.  Spansion also offered the models on their own website but the number of downloads was not recorded.  Spansion provides models in both VHDL and Verilog.  Large capacity devices are also modeled in SystemVerilog.  Although some IC companies that provide models provide only encrypted RTL models, Spansion has chosen to provide open source behavioral models that are designed for board-level verification.  These models are written by Free Model Foundry. (more…)

Free Model Foundry was founded by board designers for board designers.  We had verification problems that were not being addressed to our satisfaction by the semiconductor companies.  The EDA industry made an effort through Logic Automation and some proprietary libraries but, their business models prevented them from providing what we needed.

What we needed was:

1. Models we could read.  When a simulation reports errors, the engineer needs to determine whether he misunderstood how the component works; connected it incorrectly; or, found a bug in the model.  He cannot do this with encrypted models.
2. Models we could keep indefinitely.  We were in a mil/aero environment.  It was common for projects to be resurrected after 20 years.  Compiled models that required licensing software cannot be counted upon to be usable 5 years in the future much less 20.
3. Vendor independence.  Even if you have a simulator you like from a profitable vendor you think is wonderful, there is no guarantee that tool will be available next year.  Models must be portable which means they must conform to industry standards.

The conclusion was we had to have open source VHDL and/or Verilog models.  We also concluded that the models must be written in a style that facilitated board design.

These requirements are: (more…)

Free Model Foundry was founded expressly to promote board and system-level verification.  The founders were all board-level engineers who wanted to simulate their circuits before having them laid out, fabed and assembled as printed circuit boards.  We were working in a military/aerospace environment on designs that were considered very high speed (for that time).  We looked at acquiring models from a number of different sources but none of them met our requirements for accuracy, vendor neutrality, and longevity.  So, we created Free Model Foundry.

FMF models are architected for board verification, not chip verification.  They are frequently used by FPGA and ASIC designers to verify that their chips interface correctly with other components on their boards.  All models are open source and written in IEEE standard languages – VHDL, Verilog, and SystemVerilog.  (more…)

Component models are software.  Like any other software, sometimes they have bugs or inaccuracies.  These can enter a model do to coding errors, data sheet omissions or errors, or changes in the commercial compilers or even changes to the language standards.  In any case, although we try our best to avoid them, bugs do occur from time to time.  So, we need a way to track them and make sure they get fixed.

For this, FMF uses RT, an open source request tracker from Best Practical. The application is hosted on our own server and is accessible to both our engineering team and our customers.  This way we can ensure that once a problem is reported, (more…)