Archive for December, 2006

Language Wars Revisited for Component Modeling – VHDL or Verilog?

Monday, December 4th, 2006

I have been asked on several occasions, why FMF favors VHDL over Verilog models. At the risk (or perhaps in the hope) of reigniting the great language debates, I offer the following answer:

In the beginning, when the founders of the Free Model Foundry were trying to solve the basic problem of how to write a simulation model that would not have to be rewritten when we changed EDA vendors, the issue of language was the first consideration. Our first choice was Verilog. Cadence had recently opened it to other EDA vendors and, of importance to us, Cadence also had a static timing verification tool called Veritime. Being able to write portable models that worked in both dynamic simulation and static timing analysis was an ideal solution.

So, we set off to create the models needed to simulate a board that was being designed at TRW where we all worked. The board used mostly ECL components. We found it difficult to model a particular feature of these parts. Many had differential inputs but could be driven as single ended by connecting the unused input to the part’s Vbb output. We had parts in the design that were run single ended in one place and differentially in another. We needed a model that could sense how it was connected and behave as the actual part would. (more…)