Archive for the ‘FMF Topics’ Category

What Does Cadence’s Aquisition of Denali Mean for Denali Customers?

Friday, May 14th, 2010

The short answer to the question posed in the title is: Nobody knows.  It all depends on Cadence.  It could be good, or it could be bad.  So what’s my point?

FMF has always, since 1995, provided models as standards compliant source code.  One of the advantages to our users is that no matter what happens to FMF, you can keep using our models forever.  There are no run time licenses.  There is no compiled code to be recompiled with the next OS upgrade.  There is nothing tying a model to a particular release of a simulator.  Nothing provides the long term security of having the source code.

Now you won’t (and we haven’t) get rich with this business model.  FMF was started by engineers trying to solve the model scarcity problem.  We all had day jobs that involved designing electronic systems and we were trying to make those jobs easier.  We were also working in an industry that had 20-year product life cycles.  Stability was a requirement.  I realize that is not true in every industry.

There are other advantages to open source models.  I talk about them else elsewhere on these pages.  For now, we are reminded that long term usability is one important advantage.

Library Integration Just Got Easier

Wednesday, July 15th, 2009

In April, I wrote about the advantages of having a schematic library architecture that supports downstream processes such as functional verification.  For users of the PCB Matrix Symbol Wizard, building symbols for such a library just got easier.  In it latest release, this tool can now read FMF VHDL and Verilog models, and from them, generate schematic symbols for most popular schematic capture systems.

Generating the symbols from the simulation models makes integrating simulation and schematic capture much simpler.  The problem usually faced is that the schematic’s HDL netlister wants to use the symbol pin names to instantiate a component in the netlist.  When the symbol and model are created separately, these pin names rarely match.  Some schematic tools allow the use of a mapping file to change the netlist pin names to the desired values.  Creating that mapping file is time consuming and error prone.  However, creating the schematic symbol from the model ensures that the pin names match and eliminates the need to build and maintain mapping files.

I am happy to see PCB Matrix (a Valor company) take advantage of the open source nature of FMF models to provide new value to their customers.

Model Requests

Sunday, May 17th, 2009

We have on the FMF website, a model request form.  Many of you have already used this form and I thank you.  At this time I would like to explain what happens when an engineer requests a model.

It begins with a user filling out the on-line form.  The minimum required information is your name, email and company along with the component manufacturer’s name and the part number.  The reason for requiring the manufacturer’s name and part number are obvious.  The reason we need your information will be explained below.

When the form is submitted, an email is sent to Free Model Foundry.  When I receive the email, I first check to see if we already have a model of that part or an equivalent.  If we do I respond to the requestor suggesting he try the existing model.  If not, I check the manufacturer’s website to see if they have already published a model.  Usually, they have not.

Assuming no model is found anywhere, I send an email to someone at the manufacturer.  This is where it gets tricky.  (more…)

The Value of Integrated Schematic Libraries

Sunday, April 26th, 2009

Why talk about schematic libraries in a blog focused on system verification?  Most systems (printed circuit boards on up) are still designed using schematic capture software.

I was talking to a manager at a medical devices company the other day about his company’s schematic symbol library.  Like most libraries, it contained schematic symbols and a few “extra bits” of data such as internal part numbers and references to the PCB footprints.  I then asked if his engineers typically ran signal integrity analysis and functional verification.  He said yes, these were common tasks.  Finally, I asked how the engineers passed the correct model names into the SI tool and how they brought the VHDL/Verilog models and correct timing into the simulations and was told “Its a manual process”.

A well planned schematic library provides all the hooks needed for downstream design and verification processes including functional simulation and signal integrity analysis.  All the major “big company” design systems support these capabilities.  But none of them do it out of the box. (more…)

Don’t Forget to Attend the Embedded Systems Conference

Wednesday, March 11th, 2009

The Embedded Systems Conference – Silicon Valley runs from March 30 to April 3 at the McEnery Convention Center in San Jose, California.

This is one of the largest conferences in the electronics engineering industry.  It is also the only one I know of with a true systems focus – both hardware and software.  This year, there are over 130 sessions organized into 21 tracks.

If you have never attended this conference, look it up and see what it has to offer.  If your company is strapped for cash and can’t pay for registration, at least consider getting a free pass to the exhibits.

I will be there so feel free to stop me and say hello if you see me.