Archive for August, 2008

Tailoring Verification Models to Customer Needs

Sunday, August 17th, 2008

Last Thursday, Stephan Rosner and I gave a joint presentation to the Flash Memory Summit titled “Tailoring Verification Models to Customer Needs”.  You may download it in pdf here.  We explained that there are two design flows that require flash memory (and other) models.

One flow is for ASIC designs.  It is concerned with IP integration, code coverage, and endless verification.  It is characterized by long schedules, expensive specialized tools, and dedicated development engineers.  Denali models fit well into this environment.

The other flow is for board-level (PCB) design.  In contrast, it is concerned with correct connectivity, signal integrity (IBIS models), timing, and device behavior.  PCB design verification has short schedules, uses less expensive and more general tools, and is conducted by engineers who work across many disciplines.  Printed circuit boards are almost always designed using schematic capture.  FMF models are optimized for this environment.

Free Model Foundry models have been used in thousands of board designs to save time and money by reducing board spins.  For the IC vendors who usually fund the models, they accelerate their customers’ time to volume purchases.

FMF models are reliable because we have developed a standard method of testbench development based on the documented features of each component we model.  The testcases and expected results are documented and reviewed by the device manufacturer.  We have an on-line bug tracking system that is directly accessible by the manufacturer in case any discrepancies are found before or after the models are released.

A key differentiator is that FMF models are provided to engineers by both the manufacturers and FMF at no cost.  Since the models are written in standard VHDL and Verilog and are open source, no licenses are required and no special tools need be purchased.  This can save weeks of schedule just by eliminating the need for management signatures.  Open source allows engineers to read and understand the models when unexpected simulation results are encountered.

This unique business model helps make FMF models very widely used.  In 2007, 810,000 models were downloaded by 65,000 companies.  Spansion flash memory models were downloaded 40,000 times in a single month.

FMF open source VHDL and Verilog component models are the logical and most chosen for board-level verification.

Flash Memory Summit

Friday, August 1st, 2008

There will be a joint presentation by Free Model Foundry and Spansion, LLC. at the Flash Memory Summit in Santa Clara, California, on Wednesday, August 13.  Together we will be showing how FMF style models help engineers design new products faster and more accurately, and IC vendors sell more parts.

The conference is free so, if you are attending, please stop by and say hello after the presentation.