System Verification Blog

In April, Randy Allen of Raytheon informed me that his latest compile of the FMF models had elicited an unexpected number of warning messages from the ModelSim 6.3f VHDL compiler.  Although they were “only warnings” and the models still compiled and ran correctly, a large number of benign warnings can easy mask one that a user really cares about.

I upgraded my version ModelSim and did my own compile.  It appears that ModelSim now flags as warnings departures from the VITAL LRM that it did not care about in earlier versions.  Examination of the warning messages convinced me they were all valid.  In many of our older models, we took some short cuts to speed development that have worked fine for the past 5 to 10 years.  Now Mentor, most likely in their efforts to continually improve simulation performance, is suggesting stricter adherence to the standard.  I assume what is a warning today could become a fatal error tomorrow.

In late April we began to fix the offending code.  There were 50 or 60 models affected.  To date, 14 corrected models have been posted.  While this is not considered an urgent issue, it is FMF’s intention to updated all the flagged VHDL models over the course of the next few months.  It is part of our commitment to delivery the highest quality product we can.

If you blog about EDA or other tech design topics, or are thinking about doing so, consider attending the Bloggers’ Birds-of-a-Feather meeting at the Design Automation Conference in Anaheim next month.

The meeting will be held at 6 pm, Wednesday, June 11, in Rooms 201B and 201C at the Anaheim Convention Center. Come and meet your fans and fellow bloggers.

Are you attending the Design Automation Conference in Anaheim this year?

Our good friends at Aldec have been supports of Free Model Foundry for more years than I can remember.  Among other things, they provide us with licenses for testing our models on their Riviera simulator.  This year they have also graciously allowed me to distribute Free Model Foundry leaflets at their both on the exhibit floor.  If you would like to meet, that would be a good place to get together or exchange messages.

I do not have a schedule but will pop in and out of booth #1600 frequently.  Leave a note there or email me if you would like to meet.

Yesterday I met Vikash. He operates a relatively new website named FPGACentral. FPGA Central is created to provide a central place for FPGA/CPLD Vendors & Users to share experiences and information about FPGA Design, Development, Verification, Validation, Process, Tools & Products. Since the largest use of FMF models is for FPGA verification, we had a lot to talk about. Because the intent of both of our sites is to provide resources to engineers, we have decided to cooperate and see what synergies can be found to make your job easier.

Vikash and his associates have put a remarkable amount of work and energy into their website.  I hope to learn from them how to improve some of my own projects.

Along with SOCCentral and PCBCentral, FPGACentral should be among the bookmarks of every systems designer.

On July 17 & 18 I attended MemCon in Santa Clara. I was able to attend only the first half of the conference due to the pressures of work back in the office. The most frequently discussed topics were NAND Flash and cell phones although a number of other topics rounded out the conference. My reaction to one particular talk can be found on the Different Slants website. If you design products that use memory of any type, you might want to consider attending one of these conferences when they are in your part of the world.

Since my job at Siemens was euthanized last year, I have had time to participate in a variety of workshops and conferences. While having coffee during one of the breaks, it occurred to me how different the people are at different types of events. (more…)