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The System Verification Forum previously found elsewhere on this website has been shut down.  Last year the level of spam became intolerable.  The site was changed to make posting more difficult.  This resulted in a 90% reduction in spam but a 100% reduction in relevant posts.  Therefor, I have decided to discontinue the forum.  In… Continue reading End of the System Verification Forum

For those of you living near Silicon Valley, this is a reminder that Denali MemCon is next week.  Running Monday through Wednesday, June 22-24, it will include talks on NAND Flash Controllers, Solid State Drives (SSDs), DDR3 DRAM, and low power memory subsystems.  The conference is being held at the Hyatt on Great America Parkway… Continue reading MemCon Next Week

In case you missed it, DVCon 2009, the design and verification conference, starts Tuesday, 24 February.  The conference takes place at the DoubleTree Hotel in San Jose, California. I expect to be there all three days and would be happy to meet any FMF model users.  So if you spot me, please stop me and… Continue reading See You at DVCon

On the final day of the FPGA Summit I heard three presentations of particular interest: “Choosing the Right Flash Memory for FPGA-Based Designs” by Olivier Mardinian of Spansion.  Olivier gave a good account of the types of flash memories available and how to select one with the features you need for your design.  He also… Continue reading FPGA Summit – Day 3

Wednesday at the FPGA Summit in San Jose was interesting and worthwhile.  The morning session I attended was titled “Reconfigurable and High-Performance Computing”.  It consisted of about a half dozen presentations but, there were two I found most intriguing. The first was “FPGA Software Acceleration” by Stefan Mohl of Mitrionics.  His company offers a hardware/software… Continue reading FPGA Summit – Day 2