Archive for the ‘Uncategorized’ Category

FPGA Summit – Day 1

Tuesday, December 9th, 2008

I decided to attend the FPGA Summit at the Wyndham Hotel in San Jose this week.  It is intended to become an annual event and if it grows the way the Flash Memory Summit, run by the same people, has, it will become a big conference in a few years.

I admit I have not designed an FPGA since the Xilinx 3000 series was new.  But, since FPGA designers are among the largest user segments of FMF models, it seemed wise to see how far the technology has come.  Based on the presentations I saw from Xilinx today, it has come a long way.

Most of the talk I attended this morning was about interfacing FPGAs to SDRAMs.  The current crop of these memories, DDR2, DDR3, and QDRII, have developed highly complex interface requirements.  Partially due to their transfer rates but also due to their configurability.  Special features have been added to the Spartan and Virtex FPGAs to make the physical interface more reliable.  For example, internals delays on data inputs and be adjusted in real time to compensate for voltage and temperature changes on the board.

Xilinx also showed their Memory Interface Generator (MIG) which can generate a complete interface core for many JEDEC compliant memory components and DIMMS.  The core includes customizable controllers for initialization and operation.  Bus widths and clock speeds are selectable.

After the MIG, the Xilinx reps showed how you can debug any problems that turn up in the design with ChipScope.  Personally, I would prefer the find the problems in simulation, before building the hardware but, if some problem slips by, ChipScope looks like a great way of hunting it down.

I plan to go back tomorrow.  The Verification tutorial at 2:40 is of particular interest.  If you see me there, feel free to come up and say hi.

See you at ICCAD

Monday, November 10th, 2008

This is a quick note to let you know that I will be attending (and very briefly speaking at) the EDA Bloggers BOF at ICCAD this Wednesday (Nov. 12, 2008) at the Doubletree Hotel in San Jose. The meeting will take place in the Fir Ballroom from 4-6pm.

For more information check the SKMurphy site.

Hope to see you there.

Tailoring Verification Models to Customer Needs

Sunday, August 17th, 2008

Last Thursday, Stephan Rosner and I gave a joint presentation to the Flash Memory Summit titled “Tailoring Verification Models to Customer Needs”.  You may download it in pdf here.  We explained that there are two design flows that require flash memory (and other) models.

One flow is for ASIC designs.  It is concerned with IP integration, code coverage, and endless verification.  It is characterized by long schedules, expensive specialized tools, and dedicated development engineers.  Denali models fit well into this environment.

The other flow is for board-level (PCB) design.  In contrast, it is concerned with correct connectivity, signal integrity (IBIS models), timing, and device behavior.  PCB design verification has short schedules, uses less expensive and more general tools, and is conducted by engineers who work across many disciplines.  Printed circuit boards are almost always designed using schematic capture.  FMF models are optimized for this environment.

Free Model Foundry models have been used in thousands of board designs to save time and money by reducing board spins.  For the IC vendors who usually fund the models, they accelerate their customers’ time to volume purchases.

FMF models are reliable because we have developed a standard method of testbench development based on the documented features of each component we model.  The testcases and expected results are documented and reviewed by the device manufacturer.  We have an on-line bug tracking system that is directly accessible by the manufacturer in case any discrepancies are found before or after the models are released.

A key differentiator is that FMF models are provided to engineers by both the manufacturers and FMF at no cost.  Since the models are written in standard VHDL and Verilog and are open source, no licenses are required and no special tools need be purchased.  This can save weeks of schedule just by eliminating the need for management signatures.  Open source allows engineers to read and understand the models when unexpected simulation results are encountered.

This unique business model helps make FMF models very widely used.  In 2007, 810,000 models were downloaded by 65,000 companies.  Spansion flash memory models were downloaded 40,000 times in a single month.

FMF open source VHDL and Verilog component models are the logical and most chosen for board-level verification.

Flash Memory Summit

Friday, August 1st, 2008

There will be a joint presentation by Free Model Foundry and Spansion, LLC. at the Flash Memory Summit in Santa Clara, California, on Wednesday, August 13.  Together we will be showing how FMF style models help engineers design new products faster and more accurately, and IC vendors sell more parts.

The conference is free so, if you are attending, please stop by and say hello after the presentation.

Model Maintenance

Sunday, June 15th, 2008

In April, Randy Allen of Raytheon informed me that his latest compile of the FMF models had elicited an unexpected number of warning messages from the ModelSim 6.3f VHDL compiler.  Although they were “only warnings” and the models still compiled and ran correctly, a large number of benign warnings can easy mask one that a user really cares about.

I upgraded my version ModelSim and did my own compile.  It appears that ModelSim now flags as warnings departures from the VITAL LRM that it did not care about in earlier versions.  Examination of the warning messages convinced me they were all valid.  In many of our older models, we took some short cuts to speed development that have worked fine for the past 5 to 10 years.  Now Mentor, most likely in their efforts to continually improve simulation performance, is suggesting stricter adherence to the standard.  I assume what is a warning today could become a fatal error tomorrow.

In late April we began to fix the offending code.  There were 50 or 60 models affected.  To date, 14 corrected models have been posted.  While this is not considered an urgent issue, it is FMF’s intention to updated all the flagged VHDL models over the course of the next few months.  It is part of our commitment to delivery the highest quality product we can.