FPGA Summit – Day 1

I decided to attend the FPGA Summit at the Wyndham Hotel in San Jose this week.  It is intended to become an annual event and if it grows the way the Flash Memory Summit, run by the same people, has, it will become a big conference in a few years.

I admit I have not designed an FPGA since the Xilinx 3000 series was new.  But, since FPGA designers are among the largest user segments of FMF models, it seemed wise to see how far the technology has come.  Based on the presentations I saw from Xilinx today, it has come a long way.

Most of the talk I attended this morning was about interfacing FPGAs to SDRAMs.  The current crop of these memories, DDR2, DDR3, and QDRII, have developed highly complex interface requirements.  Partially due to their transfer rates but also due to their configurability.  Special features have been added to the Spartan and Virtex FPGAs to make the physical interface more reliable.  For example, internals delays on data inputs and be adjusted in real time to compensate for voltage and temperature changes on the board.

Xilinx also showed their Memory Interface Generator (MIG) which can generate a complete interface core for many JEDEC compliant memory components and DIMMS.  The core includes customizable controllers for initialization and operation.  Bus widths and clock speeds are selectable.

After the MIG, the Xilinx reps showed how you can debug any problems that turn up in the design with ChipScope.  Personally, I would prefer the find the problems in simulation, before building the hardware but, if some problem slips by, ChipScope looks like a great way of hunting it down.

I plan to go back tomorrow.  The Verification tutorial at 2:40 is of particular interest.  If you see me there, feel free to come up and say hi.

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