FPGA Summit – Day 2

Wednesday at the FPGA Summit in San Jose was interesting and worthwhile.  The morning session I attended was titled “Reconfigurable and High-Performance Computing”.  It consisted of about a half dozen presentations but, there were two I found most intriguing.

The first was “FPGA Software Acceleration” by Stefan Mohl of Mitrionics.  His company offers a hardware/software system for accelerating software using reconfigurable a FPGA based server.  It begins with a C like language called Mitrion-C that facilitates writing parallelizable code.  The code is than passed through a compiler where it is optimized and reduced to a bit stream for a high end Altera or Xilinx FPGA.  The FPGA resides on a special motherboard in the server along with a standard AMD or Intel processor.  A graphical debugger is included.  The FPGA executes the code based on data dependencies not instruction ordering.  Of course your performance improvement is dependent on the algorithms you are trying to accelerate.

The other presentation I found fascinating was titled “Dimensions in Reconfigurable Computing” by Joseph Hassoun of Element CXI.  This company has created an IC called the ECA-64 that contains a processing fabric comprised of heterogeneous elements.  Each element can be an ALU, Multiplier, etc.  Development and configuration software are provided and a development board is also available.

The afternoon session was titled “FPGA Verification”.  Although all the presenters did great jobs with their material, I was disappointed that none of them mentioned verification of FPGAs in the context of the boards they are designed into.  I could speculate as why system verification gets so little attention but will save that for another post.

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