FMF/Spansion Presentation – Part 2

Board-level designers and ASIC designers need verification for the same reasons – to reduce development time and avoid design spins.  As in ASIC designs, interconnect delays and timing closure have become factors in board design.  Unfortunately, most vendor supplied component models are derived from their RTL models, they do not allow back-annotation of interconnect delays. … Continue reading FMF/Spansion Presentation – Part 2

Categorized as FMF Topics

FPGA Summit – Day 3

On the final day of the FPGA Summit I heard three presentations of particular interest: “Choosing the Right Flash Memory for FPGA-Based Designs” by Olivier Mardinian of Spansion.  Olivier gave a good account of the types of flash memories available and how to select one with the features you need for your design.  He also… Continue reading FPGA Summit – Day 3

FPGA Summit – Day 2

Wednesday at the FPGA Summit in San Jose was interesting and worthwhile.  The morning session I attended was titled “Reconfigurable and High-Performance Computing”.  It consisted of about a half dozen presentations but, there were two I found most intriguing. The first was “FPGA Software Acceleration” by Stefan Mohl of Mitrionics.  His company offers a hardware/software… Continue reading FPGA Summit – Day 2

FPGA Summit – Day 1

I decided to attend the FPGA Summit at the Wyndham Hotel in San Jose this week.  It is intended to become an annual event and if it grows the way the Flash Memory Summit, run by the same people, has, it will become a big conference in a few years. I admit I have not… Continue reading FPGA Summit – Day 1