Archive for December, 2008

FMF/Spansion Presentation – Part 2

Wednesday, December 17th, 2008

Board-level designers and ASIC designers need verification for the same reasons – to reduce development time and avoid design spins.  As in ASIC designs, interconnect delays and timing closure have become factors in board design.  Unfortunately, most vendor supplied component models are derived from their RTL models, they do not allow back-annotation of interconnect delays.  This limits their usefulness in timing verification.

FMF models are architected specifically for board-level verification, so they have a feature set optimized to that purpose.  For that reason, they have been used in thousands of board designs where they have saved time and design spins.  If you are a vendor that provides FMF models to your customers, this brings you production volume purchases sooner and helps get your components designed into the product.

Free Model Foundry usually creates models directly from published (or preliminary) data sheets.  (more…)

FPGA Summit – Day 3

Thursday, December 11th, 2008

On the final day of the FPGA Summit I heard three presentations of particular interest:

“Choosing the Right Flash Memory for FPGA-Based Designs” by Olivier Mardinian of Spansion.  Olivier gave a good account of the types of flash memories available and how to select one with the features you need for your design.  He also talked about the support provided by Spansion to help you design in their components.  This includes device drivers, programmers, a complete set of models (VHDL, Verilog, and IBIS) and app notes.  Spansion and FMF have worked together for several years now so, I know how hard they work to make life easier for systems designers.

“Automating FPGA-Based System Design” by Nagesh Gupta of Taray.  Nagesh talked about his company’s & Circuits product which makes optimizing FPGA pinouts much faster and easier.  The tool has knowledge of FPGA I/O capabilities and allows an engineer to graphically assign a pinout that works for both FPGA and PCB routing.  This tool provides its own graphical representation of the PCB layout and ratsnest so it is vendor neutral regarding the users schematic capture and PCB layout software.  When I was CAE manager at Acuson, my engineers wrote an application with similar capabilities minus the nice graphical interface.  If a commercial package like this had been available, we would have purchased it instead.

“Effective FPGA/PCB Co-Design” by Bob Potock of Mentor Graphics.  Bob presented a tool that was very much like 7 Circuits.  The primary difference seemed to be that it was tightly coupled to Mentor’s DxDesigner and Expedition tools.  Having tools that are tightly coupled can be a significant productivity booster when everything works.  If they don’t work or if you have multiple tool sets, something vendor agnostic mat serve you better.  Both tools looked good.

Overall, I would say the conference was a success – at least from an attendees perspective.  There was something over 500 people registered.  I don’t have the actual attendance numbers.  I am sure it will grow next year – the economy willing.

FPGA Summit – Day 2

Wednesday, December 10th, 2008

Wednesday at the FPGA Summit in San Jose was interesting and worthwhile.  The morning session I attended was titled “Reconfigurable and High-Performance Computing”.  It consisted of about a half dozen presentations but, there were two I found most intriguing.

The first was “FPGA Software Acceleration” by Stefan Mohl of Mitrionics.  His company offers a hardware/software system for accelerating software using reconfigurable a FPGA based server.  It begins with a C like language called Mitrion-C that facilitates writing parallelizable code.  The code is than passed through a compiler where it is optimized and reduced to a bit stream for a high end Altera or Xilinx FPGA.  The FPGA resides on a special motherboard in the server along with a standard AMD or Intel processor.  A graphical debugger is included.  The FPGA executes the code based on data dependencies not instruction ordering.  Of course your performance improvement is dependent on the algorithms you are trying to accelerate.

The other presentation I found fascinating was titled “Dimensions in Reconfigurable Computing” by Joseph Hassoun of Element CXI.  This company has created an IC called the ECA-64 that contains a processing fabric comprised of heterogeneous elements.  Each element can be an ALU, Multiplier, etc.  Development and configuration software are provided and a development board is also available.

The afternoon session was titled “FPGA Verification”.  Although all the presenters did great jobs with their material, I was disappointed that none of them mentioned verification of FPGAs in the context of the boards they are designed into.  I could speculate as why system verification gets so little attention but will save that for another post.

FPGA Summit – Day 1

Tuesday, December 9th, 2008

I decided to attend the FPGA Summit at the Wyndham Hotel in San Jose this week.  It is intended to become an annual event and if it grows the way the Flash Memory Summit, run by the same people, has, it will become a big conference in a few years.

I admit I have not designed an FPGA since the Xilinx 3000 series was new.  But, since FPGA designers are among the largest user segments of FMF models, it seemed wise to see how far the technology has come.  Based on the presentations I saw from Xilinx today, it has come a long way.

Most of the talk I attended this morning was about interfacing FPGAs to SDRAMs.  The current crop of these memories, DDR2, DDR3, and QDRII, have developed highly complex interface requirements.  Partially due to their transfer rates but also due to their configurability.  Special features have been added to the Spartan and Virtex FPGAs to make the physical interface more reliable.  For example, internals delays on data inputs and be adjusted in real time to compensate for voltage and temperature changes on the board.

Xilinx also showed their Memory Interface Generator (MIG) which can generate a complete interface core for many JEDEC compliant memory components and DIMMS.  The core includes customizable controllers for initialization and operation.  Bus widths and clock speeds are selectable.

After the MIG, the Xilinx reps showed how you can debug any problems that turn up in the design with ChipScope.  Personally, I would prefer the find the problems in simulation, before building the hardware but, if some problem slips by, ChipScope looks like a great way of hunting it down.

I plan to go back tomorrow.  The Verification tutorial at 2:40 is of particular interest.  If you see me there, feel free to come up and say hi.

FMF/Spansion Presentation – Part I

Wednesday, December 3rd, 2008

As mentioned in “Tailoring Verification Models to Customer Needs“, in August 2008, Stephan Rosner of Spansion and I gave a joint presentation at the Flash memory Summit in San Jose.  My intent is to provide the content of that presentation spread over several short posts.

There are two general design verification flows used in digital electronic design.  The one the that receives most of the press, because it can be very time consuming and expensive, is the ASIC flow.  It is characterized by specialized tools, low levels of abstraction, and often, encrypted models of purchased IP.  Because of the low level of abstraction involved, ASIC simulations seek out low level logic flaws and can be very slow.  Errors found and take a long time to resolve.

The other flow, the one FMF was founded to support, is the board or system flow.  This flow is characterized by standards based tools, high levels of abstraction and, with a few exceptions, open source models of off-the-shelf ICs.  (more…)