Board-level designers and ASIC designers need verification for the same reasons – to reduce development time and avoid design spins. As in ASIC designs, interconnect delays and timing closure have become factors in board design. Unfortunately, most vendor supplied component models are derived from their RTL models, they do not allow back-annotation of interconnect delays. This limits their usefulness in timing verification.
FMF models are architected specifically for board-level verification, so they have a feature set optimized to that purpose. For that reason, they have been used in thousands of board designs where they have saved time and design spins. If you are a vendor that provides FMF models to your customers, this brings you production volume purchases sooner and helps get your components designed into the product.
Free Model Foundry usually creates models directly from published (or preliminary) data sheets. (more…)