FMF/Spansion Presentation – Part 2

Board-level designers and ASIC designers need verification for the same reasons – to reduce development time and avoid design spins.  As in ASIC designs, interconnect delays and timing closure have become factors in board design.  Unfortunately, most vendor supplied component models are derived from their RTL models, they do not allow back-annotation of interconnect delays.  This limits their usefulness in timing verification.

FMF models are architected specifically for board-level verification, so they have a feature set optimized to that purpose.  For that reason, they have been used in thousands of board designs where they have saved time and design spins.  If you are a vendor that provides FMF models to your customers, this brings you production volume purchases sooner and helps get your components designed into the product.

Free Model Foundry usually creates models directly from published (or preliminary) data sheets.  A methodology has been developed allowing us to document all the test cases the model will be checked against so the vendor can determine if any cases were missed or should be excluded.  Having a uniform test methodology improves both our productivity and the quality of our results.

In most cases a VHDL testbench is developed for the VHDL model and then copied and modified to instantiate the Verilog model so both models are run against the same testbench.  The testbenches are self-checking.  They are run in non-graphical mode with timing back-annotation.  As they run they list the test being run and end with a statement that there either were or were not any errors found.

We do not publish the testbenches because the purpose of our models is not to simulate a single component but to verify a design using that component.  However, when requested, FMF will furnish testbenches to engineers who need to create derivative models or have other uses for them.

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