System Verification Blog

Here are my thoughts on what were for me, the top three sessions at DVCon.

“Techononmics of Verification” by Aart de Geus.

If you have ever attended one of Aart’s talks, you already know he is a fanastic speaker.  Through amusing graphics and wry humor he showed how global practices and financial instruments created a “vicious system” with way too much feedback.  Now the output is headed for the negative rail and we are all looking at a “standard of living reset”.  It all seems so clear in retrospect.

Then there was the panel session titled “EDA: Dead or Alive?” moderated by Peggy Aycinena.  This was a panel of seven EDA CEOs and VPs.  Peggy did a excellent job moderating the group and forcing upon them a level of discipline they should all take back to their offices. (more…)

In December, Largine responded to a previous post by asking for more information about FMF’s modeling style.  I will try to answer here primarily by referencing more detailed sources of information.

First, one might ask why there should even be an “FMF style” for component models.  The answer is that by making models uniform in appearance and architecture, they can be more easily understood and modified by users and maintainers.  Once you become familiar with one model, all the others are easier to learn because they look alike and have the same structure.

There are two aspects to the FMF style: aesthetics and architecture.  These are both covered in an paper written mostly by Ray Steele in 1999 and still followed today.

One might think that aesthetics are not important.  I strongly disagree.  They may be unimportant in a project done by a single engineer and in which the code will never be (more…)

This is the sixth and final installment of the FMF/Spansion presentation given at the Flash Memory Summit of August 2008 in Santa Clara California.  If you are just tuning in, the first installment was posted in December 2008.

It has taken a long time but, most IC companies have seen the advantages of providing simulation models of their components.  For engineers who use board-level verification in their design process, vendor provided models facilitate faster, more accurate development and shorter time to market.  Unfortunately, not all vendors are providing models and many of those that do are modeling only a subset of their product lines.

Spansion, on the other hand, is providing models of their entire portfolio of flash memories.  The response from engineers has been enthusiastic.  In 2007, downloads of Spansion flash memory models exceeded 40,000 per month just from the FMF website.  Spansion also offered the models on their own website but the number of downloads was not recorded.  Spansion provides models in both VHDL and Verilog.  Large capacity devices are also modeled in SystemVerilog.  Although some IC companies that provide models provide only encrypted RTL models, Spansion has chosen to provide open source behavioral models that are designed for board-level verification.  These models are written by Free Model Foundry. (more…)

Free Model Foundry was founded by board designers for board designers.  We had verification problems that were not being addressed to our satisfaction by the semiconductor companies.  The EDA industry made an effort through Logic Automation and some proprietary libraries but, their business models prevented them from providing what we needed.

What we needed was:

1. Models we could read.  When a simulation reports errors, the engineer needs to determine whether he misunderstood how the component works; connected it incorrectly; or, found a bug in the model.  He cannot do this with encrypted models.
2. Models we could keep indefinitely.  We were in a mil/aero environment.  It was common for projects to be resurrected after 20 years.  Compiled models that required licensing software cannot be counted upon to be usable 5 years in the future much less 20.
3. Vendor independence.  Even if you have a simulator you like from a profitable vendor you think is wonderful, there is no guarantee that tool will be available next year.  Models must be portable which means they must conform to industry standards.

The conclusion was we had to have open source VHDL and/or Verilog models.  We also concluded that the models must be written in a style that facilitated board design.

These requirements are: (more…)

Free Model Foundry was founded expressly to promote board and system-level verification.  The founders were all board-level engineers who wanted to simulate their circuits before having them laid out, fabed and assembled as printed circuit boards.  We were working in a military/aerospace environment on designs that were considered very high speed (for that time).  We looked at acquiring models from a number of different sources but none of them met our requirements for accuracy, vendor neutrality, and longevity.  So, we created Free Model Foundry.

FMF models are architected for board verification, not chip verification.  They are frequently used by FPGA and ASIC designers to verify that their chips interface correctly with other components on their boards.  All models are open source and written in IEEE standard languages – VHDL, Verilog, and SystemVerilog.  (more…)