Category: FMF Topics

Component models are software.  Like any other software, sometimes they have bugs or inaccuracies.  These can enter a model do to coding errors, data sheet omissions or errors, or changes in the commercial compilers or even changes to the language standards.  In any case, although we try our best to avoid them, bugs do occur… Continue reading FMF/Spansion Presentation – Part 3

Board-level designers and ASIC designers need verification for the same reasons – to reduce development time and avoid design spins.  As in ASIC designs, interconnect delays and timing closure have become factors in board design.  Unfortunately, most vendor supplied component models are derived from their RTL models, they do not allow back-annotation of interconnect delays. … Continue reading FMF/Spansion Presentation – Part 2

As mentioned in “Tailoring Verification Models to Customer Needs“, in August 2008, Stephan Rosner of Spansion and I gave a joint presentation at the Flash memory Summit in San Jose.  My intent is to provide the content of that presentation spread over several short posts. There are two general design verification flows used in digital… Continue reading FMF/Spansion Presentation – Part I

Today I catapulted the Free Model Foundry website into the twentieth century by adding its first graphic.  Yeah, it has sported company logos since its beginning but this is an actual picture. Place graphics on websites has been the norm for a long time now.  However, as an older engineer, my orientation has always been… Continue reading A Picture is Prettier than a Thousand Words

Today, someone asked in the forum what restrictions are placed on the use of FMF models. FMF models are as open as we can make them. They are distributed as source code and are licensed under the Gnu Public License (GPL). There is only one restriction: If you choose to sell, distribute or publish one… Continue reading How “Open” are FMF Models?