FMF Modeling Style

In December, Largine responded to a previous post by asking for more information about FMF’s modeling style.  I will try to answer here primarily by referencing more detailed sources of information.

First, one might ask why there should even be an “FMF style” for component models.  The answer is that by making models uniform in appearance and architecture, they can be more easily understood and modified by users and maintainers.  Once you become familiar with one model, all the others are easier to learn because they look alike and have the same structure.

There are two aspects to the FMF style: aesthetics and architecture.  These are both covered in an paper written mostly by Ray Steele in 1999 and still followed today.

One might think that aesthetics are not important.  I strongly disagree.  They may be unimportant in a project done by a single engineer and in which the code will never be seen by anyone else but, that is not the case for component models.  FMF component models are used for decades.  For both designing components in to a new design and for designing them out when they become obsolete.  They are downloaded and utilized by tens of thousands of engineers around the world.  Because they are open source models, it is expected that engineers will read them.  Under these circumstances, readability is a highly valued quality.  Although some of the conventions followed in FMF models, such as capitalization and indentation rules, may seem arbitrary, it is the consistency of their application that makes them valuable.

The other aspect of style is architecture.  Having a consistent architecture not only makes the models more understandable, it facilitates code reuse.  New models often contain sections of code cut and pasted from previous models.

FMF VHDL models incorporate the VITAL (IEEE 1076.4) specification and libraries.  That dictates much of our model architecture.  Other aspects, such as scalar bus interfaces, are based on making the models compatible with schematic capture systems and PCB timing backannotation.  Much of this is explained in Ray Steele’s paper.

Readers looking for complete details regarding FMF’s modeling methodology are referred to the book “ASIC and FPGA Verification: A Guide to Component Modeling” available in hard cover (and sometimes as an ebook) from

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