FMF/Spansion Presentation – Part 4

Free Model Foundry was founded expressly to promote board and system-level verification.  The founders were all board-level engineers who wanted to simulate their circuits before having them laid out, fabed and assembled as printed circuit boards.  We were working in a military/aerospace environment on designs that were considered very high speed (for that time).  We looked at acquiring models from a number of different sources but none of them met our requirements for accuracy, vendor neutrality, and longevity.  So, we created Free Model Foundry.

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FMF models are architected for board verification, not chip verification.  They are frequently used by FPGA and ASIC designers to verify that their chips interface correctly with other components on their boards.  All models are open source and written in IEEE standard languages – VHDL, Verilog, and SystemVerilog. 

Open source allows engineers to look inside the model when trying to determine why a simulation does not produce the expected results.  It also means that once you have one of our models, you can keep it forever.  It is not tied to a license that can expire or an operating system that will be replaced.

Using IEEE standard languages makes the models portable between simulation tools from different vendors.  You can use Aldec today and Mentor tomorrow.  Just recompile and continue.

The open source requirement also drove us to a unique business model.  We charge for the creation of new models but, once they are created, we make them available to engineers at no cost.  You do not even have to register (though it is nice when you do).

So who uses FMF models?

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It seems like everyone.  In 2007, FMF models were downloaded to over 65,000 sites worldwide.  The number of models downloaded was about 810,000.  The numbers have been growing every year.

Engineers request FMF models from their IC suppliers.  The more that happens, the more models we will be able to provide to you.

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