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System Verification Blog

Where a system is more than one chip

Month: January 2010

End of the System Verification Forum

The System Verification Forum previously found elsewhere on this website has been shut down.  Last year the level of spam became intolerable.  The site was changed to make posting more difficult.  This resulted in a 90% reduction in spam but a 100% reduction in relevant posts.  Therefor, I have decided to discontinue the forum.  In… Continue reading End of the System Verification Forum

Published January 31, 2010
Categorized as Uncategorized

Author

Richard Munden began his career in EDA in 1988. He soon became interested in board and system level simulation and has been beating that drum ever since. He is auther of the best selling (and only) book published on VHDL/VITAL and component modeling, "ASIC and FPGA Verification: A Guide to Component Modeling" (Morgan Kaufman Publishers, ISBN: 0-12-510581-9). He believes everyone should have two copies. View Rick Munden's profile on LinkedIn

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