For any who do not know John Cooley, he is best described as one of the more colorful characters upon the EDA landscape. He began his “East Coast Synopsys Users Group“ (ESNUG) around 1991 to discuss workarounds to the Synopsys Design Compiler and now has 23,000 subscribers and an EDA website called DeepChip. You can… Continue reading John Cooley and the Denali Memory Model Monopoly

FMF recently had a major IC company contact us to say they wanted to do business with us and have us begin modeling some of their components. We had been trying to sell our services to this company for nine years so I needed to know why they were coming around now. The answer was… Continue reading The Need to Exceed

An engineer and user of FMF (www.FreeModelFoundry.com) component models was recently having difficulties simulating a design that included a large amount of memory. His simulations would die during elaboration because his PC did not have enough memory. He was advised by an applications engineer from his simulator vendor that Verilog models would consume less computer… Continue reading VHDL vs Verilog Model Footprints

First, lets understand what we mean by models. We will restrict this discussion to digital ICs. There are at least three distinct types of models system designers might need. Signal integrity models are needed to verify that the traces connecting the different parts on the board and across the backplane will carry the signals from… Continue reading Why Should IC Companies Supply Models?

Back in 1995, the EDA companies were all touting top-down design as the methodology that would overcome the unending rise in product complexity. They were also pushing frameworks at that time. Frameworks are rarely spoken of today and, when they are, it is usually in a sarcastic manner. Top-down design however, would seem to be… Continue reading The Mythical Top-Down Design Flow