Now that SystemC has been around for a few years, it seems the hype about it is somewhat diminished. FMF has offered SystemC modeling services for some time but we have never had any inquiries much less takers. This leads me to the question, “From a board-level modeling perspective, what advantage does SystemC offer over VHDL or SystemVerilog?” Is there any?
If you know or have an opinion, please let me hear from you.
I like your VHDL model so much.
But I am wondering how can I find a DDR SDRAM VHDL model in your website?
Thank you so much.
David,
The easiest way to find a DDR model is to type “DDR” into the search box.
If you want to model a system, I believe that either VHDL or straight C++ is best, depending on what exactly you need to model.
Now when you model to verify a chip, the question must be answered separately.
SystemC versus Systemverilog:
SystemC is based on C++, so AS FAST AS YOU CAN GET ABOVE SYSTEMC, you are far better off then System Verilog. SystemVerilog is just too green and saddled with Verilog to be of much use beyond a basic system.
SystenC versus VHDL:
While I greatly respect VHDL as a hardware language, verification comes from a programming perspective so C++ is a better choice. Unfortunately, SystemC fights you in many ways and makes it difficult to design a flexible, well understood system.
Thats my two cents.
Complexity is the main cons of SC.
They want to offer too much in SC the language is too huge….