An engineer and user of FMF (www.FreeModelFoundry.com) component models was recently having difficulties simulating a design that included a large amount of memory. His simulations would die during elaboration because his PC did not have enough memory. He was advised by an applications engineer from his simulator vendor that Verilog models would consume less computer memory than VHDL models.
This seemed contrary to my personal experience. I wanted to say the applications engineer was wrong but, I hate making a fool of myself in public (again) and did not have the numbers to back me up. I told the engineer I would get the numbers and report back to him.
Which language has the smaller footprint for memory models? I ran some tests to find out. A summary of the results are presented below. A full report is available in a white paper on the FMF website.
I started with pair of 1Gb flash memory parts we just modeled for Spansion. These two parts are the same but in 8-bit and 16-bit wide versions. We wrote 4 models for each part. VHDL models with static and dynamic memory allocation, Verilog with static memory allocation and SystemVerilog with dynamic memory allocation.
The first tests measured the memory footprint of the bare model – no testbench, no SDF backannotation, and no stimulus. I was surprised to find that although the VHDL models did have a smaller footprint (for static allocation), it was not much smaller – just about 5%. The dynamic VHDL and dynamic SystemVerilog models were the same size.
Then I looked inside the models and realized that FMF had used the same memory representation method in both the VHDL and Verilog models. This method stores memory words as integers rather than arrays of std_logic_vector or registers. It is considerably more computer memory efficient than the traditional methods. Just how much more efficient depends on the device word width – wider words (up 30-bits) are better than narrower words. This can be seen in the numbers below.
Then curiosity struck. Are VHDL/Verilog memory ratios preserved in a full blown simulation? Only one way to find out. I compiled the testbenches and ran the full testsuite on each model. This time, I measured not just the computer memory footprint of the simulation but also the CPU run times. To keep thing simple, all the simulations were run in batch mode. Full timing with SDF backannotation was included. Then I repeated it all with a second vendor’s simulator. The results are, shall we say, interesting.
| 1Gb x8 model | |||||
| Simulator A | Simulator B | ||||
| footprint size | CPU run time | footprint size | CPU run time | ||
| static allocation | VHDL | 1621MB | 68 Sec | 1255MB | 36 sec |
| static allocation | Verilog | 2225MB | 277 Sec | N/A | N/A |
| dynamic allocation | VHDL | 25MB | 39 Sec | 203MB | 100 sec |
| dynamic allocation | SystemVerilog | 25MB | 210 Sec | N/A | N/A |
| 1Gb x16 model | |||||
| static allocation | VHDL | 829MB | 21 Sec | 727MB | 19 sec |
| static allocation | Verilog | 1137MB | 94 Sec | 1208MB | 710 sec |
| dynamic allocation | VHDL | 25MB | 16 Sec | 195MB | 34 sec |
| dynamic allocation | SystemVerilog | 25MB | 54 Sec | N/A | N/A |
Some of these numbers I can explain and some I can’t. The footprint size difference between the x8 and the x16 models is what I would expect – about half. The run time difference though, is up to twice that. Why?
The shocker for many people should be the run time difference between VHDL and Verilog or SystemVerilog. In these tests we see VHDL running 3 to 5 times faster than Verilog. This tells me that even companies that use Verilog for chip design, may want to consider VHDL for board-level verification.
All these tests used non-synthesizable behavioral models. The result should not be considered applicable to RTL or gate-level models or simulations.