Category: FMF Topics

Now that SystemC has been around for a few years, it seems the hype about it is somewhat diminished. FMF has offered SystemC modeling services for some time but we have never had any inquiries much less takers. This leads me to the question, “From a board-level modeling perspective, what advantage does SystemC offer over… Continue reading SystemC – What Is It Good For?

I have been asked on several occasions, why FMF favors VHDL over Verilog models. At the risk (or perhaps in the hope) of reigniting the great language debates, I offer the following answer: In the beginning, when the founders of the Free Model Foundry were trying to solve the basic problem of how to write… Continue reading Language Wars Revisited for Component Modeling – VHDL or Verilog?

Over the years, I have discovered that many engineers think that behavioral and register transfer level models are the same. On closer questioning I find that these engineers are unware that a higher level of abstraction exists above RTL. Well there is, and when it comes to board and system level design and verification, the… Continue reading Behavioral Modeling vs RTL

This article attempts to provide some background information about FMF in order to give some perspective on why the company was founded and why it still exists today. In short, how we got to where we are. In the early 1990s, the three founders of FMF, Luis Garcia, Russ Vreeland, and Richard Munden, were engineers… Continue reading FMF Origins

Engineers often ask “Do I have to use timing with FMF models?” The answer, as usual, is “It depends”. In most cases, the engineer is working on an ASIC or FPGA which they are simulating at the register transfer level. The FPGA model has no timing, cycle accurate simulation is sufficient so, why should any… Continue reading Why You Need Timing in Your Simulation