FMF Origins

This article attempts to provide some background information about FMF in order to give some perspective on why the company was founded and why it still exists today. In short, how we got to where we are.

In the early 1990s, the three founders of FMF, Luis Garcia, Russ Vreeland, and Richard Munden, were engineers at TRW in Redondo Beach California. We were all involved in systems and board design. We found there that board-level simulation caught problems that would otherwise have to be debuged and corrected in the lab and might even cause board spins. The only drawback was the amount of time required to create the component models that were missing from our EDA vendor supplied libraries.

Being good engineers, we asked ourselves “How can we dodge this work?” We called a few of our component suppliers and suggested they should provide simulation models for their products just like they provided datasheets. In those days all the digital simulators were proprietary and any model written for one of them could not work on any other. The component vendors were aware of this and told us they did not have the resources to write models for every simulator and rather than have to choose which simulator they would support, they prefered to support none of them.

The next thing we tried was getting a common model format through a standards organization. At that time, the CAD Framework Initiative (CFI) had a Component Information Representation (CIR) technical working group. I joined and fatihfully attended meeting and documents for 2 years. Evently, I realized that the component vendors were sending only their tech pubs people and that all that could be expected to come out of the group was electronic datasheets.

Then, in 1994, Russ looked into the VHDL Initiative Toward ASIC Libraries (VITAL). VHDL was becoming a common, standard simulator at that time. However, for gate-level simulation, it was too slow. The intent of VITAL was to define a set of primitives, tables, and a timing backannotation mechanism that could be optimized by the EDA vendors to accelerate gate-level ASIC simulations. Something similar had already been done for Verilog, creating Verilog-XL, but Verilog was still a proprietary language back then. Russ determined that VITAL had just what we needed to create portable, timing independent component models. Timing independence means we do not have to create a new model every time component comes out in a faster technology or new speed grade. We experimented, writing a couple of dozen models of mostly ECL components, and found it did the trick.

We could now write component models and continue using them when we changed EDA vendors. That was a good start but we were still writing the models ourselves. VITAL/VHDL was still too new for the component vendors to jump on. So, in 1995, we started the Free Model Foundation. We were hoping to do for component models what the Free Software Foundation was doing for software. We incorporated in California and convinced TRW to allow us to post the models we created while working on our various projects. Because we decide to publish source code models, being much more useful than encrypted models, it meant not following the traditional EDA business model of collecting money from each user. The idea was we would post our models for free download and other engineers would create models in the same style and contribute them to the community. Eventually, the component vendors would catch on and simply provide the models so engineers could spend all their time designing the parts into systems and buy lots of parts.

Few businesses work out according to their initial concepts. In 1997, the state asked us to take the word “foundation” out of our name. Wanting to keep the FMF moniker, we became the Free Model Foundry. We did not get the number of contributed models we expected. We do receive and publish them from time to time but 99% of our models are internally generated. However, we have received more commercial support than planned. At first, it was systems design companies that needed models for their own use and did not mind sharing them. Later as the IC manufacturers caught on to the need for models, some of them began to contract us as a way of outsourcing the effort. Providing another distribution channel didn’t hurt either.

Along the way Verilog became a standard. Some components cannot be modeled well in Verilog, but SystemVerilog seems to add the missing capabilities. We were still reluctant to model in Verilog/SystemVerilog because of portability problems found. It is difficult to write a model that works properly with multiple Verilog simulators. However, our customers have asked for it so we provide Verilog models that work with simulator from Cadence and Mentor.

Today (October 2006) there are VHDL and Verilog models and timing files covering more than 10,000 orderable part numbers. New models and bug fixes and upgrades to old models are released every week. If you do not find what you need, please contact our commerical modeling arm at: to see how we can create a model for you.

Rick Munden

1 comment

  1. looks like a good site for the future. only had 1 of 4 mems I needed though. I will contact the mfgrs about contracting you. I was looking for a quick endrun of a denali license problem and will consider you in the future.

    thx for your comments on deepchip that led me here this AM

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