August 8th, 2009
The 2009 Flash Memory Summit starts Tuesday and runs August 9-11 at the Santa Clara Convention Center in California. Begun in 2006, this conference has grown tremendously reflecting both the importance of flash memory in electronic design and the success of the organizers in putting together a program that provides values to an ever increasing number of attendees.
If you design anything that uses flash – and I would be hard put to think of something that doesn’t – this is a conference for you. Unfortunately, I will be able to attend only on Tuesday. There is a conflict with OpenSource World, another important event for me, on Wednesday and Thursday.
July 30th, 2009
Being glued to a booth, I did not see as much of DAC as I would have liked. However, I still managed to see many old friends and meet a couple of new ones. That is what DAC has become for me – an event for renewing exisitng relationships and starting new ones.
This social aspect of DAC was acknowledged in a track titled “Conversation Central” which had its own small room near the Synopsys booth. Sean Murphy, Harry Gries, John Cooley and others led sessions centered on communications and media. Unfortunately, I was able to attend only one of them.
I have not seen the attendance numbers for this year’s DAC but it felt very low.
A crowd-free DAC in 2009
This picture was taken about 11 am Wednesday. It looks like the exhibitors may outnumber the attendees. There were about twice as many people on free Monday.
I can think of many reasons for the low turn out – but I would rather hear what you think.
July 29th, 2009
The Design Automation Conference, being held this week in San Francisco, seems a subdued affair from those a few years ago. This year, I am helping a friend man the FTL booth due to the scheduled person coming down with the dreaded swine flu. Although I have walked around and seen al the other booths, time has not allowed a detailed examination of any of their offerings.
However, I was impressed by one company and its CEO. Micro Magic is in the booth next to FTL so there was opportunity to learn what they are about. They have a suite of IC layout tools that is impressive in its performance and capacity. I will not go into detail, I have to catch a train back to DAC, but I recommend checking them out if layout is your thing. The CEO, Mark Santoro, is a straight talking guy who was able to push all my hot buttons – and don’t even do layout.
If you are around DAC today (Wednesday) please stop by the FTL booth and say hello.
July 15th, 2009
In April, I wrote about the advantages of having a schematic library architecture that supports downstream processes such as functional verification. For users of the PCB Matrix Symbol Wizard, building symbols for such a library just got easier. In it latest release, this tool can now read FMF VHDL and Verilog models, and from them, generate schematic symbols for most popular schematic capture systems.
Generating the symbols from the simulation models makes integrating simulation and schematic capture much simpler. The problem usually faced is that the schematic’s HDL netlister wants to use the symbol pin names to instantiate a component in the netlist. When the symbol and model are created separately, these pin names rarely match. Some schematic tools allow the use of a mapping file to change the netlist pin names to the desired values. Creating that mapping file is time consuming and error prone. However, creating the schematic symbol from the model ensures that the pin names match and eliminates the need to build and maintain mapping files.
I am happy to see PCB Matrix (a Valor company) take advantage of the open source nature of FMF models to provide new value to their customers.
July 8th, 2009
The 46th annual Design Automation conference takes place at the Moscone Center in San Francisco July 27-30. It will be the 20th conference for me and I have to admit I am not as excited about going as I was in the early ’90s.
Back then it was a much broader conference with papers about FPGA design and PCB interconnect timing modeling. Now there is little other than chip design. Not that chip design isn’t exciting – its just not what I do. I suspect most EEs are not chip designers either. However, I suspect the bulk of the revenue being taken in by the EDA companies is related to chip design.
That said, I will still attend DAC this year. It remains the single best conference for meeting industry folk that I tend to meet only once a year.
While I head off to DAC each year with mild enthusiasm and low expectations, I have always come back with more new contacts and useful information than I had anticipated. So, once again, I will see you at DAC.
Don’t miss the Denali party!